The disclosure relates to a semiconductor device, and more particularly, to an integrated circuit (IC) configured to gather and store debugging data, an application processor (AP), and an electronic device including the AP.
With an increase in the integration density of semiconductor chips, it would take much time and a lot of resources to test the semiconductor chips. A Design For Testability (DFT) technique has widely been used to maintain the quality of semiconductor chips and increase testing efficiency. A scan test technique may occupy a large part of the DFT technique. By using the scan test technique, errors in hardware and/or software of a System on Chip (SoC) may be debugged through a scandump method.